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1 file number 2456.5 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. http://www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999 HSP48908 two dimensional convolver the intersil HSP48908 is a high speed two dimensional convolver which provides a single chip implementation of a video data rate 3 x 3 kernel convolution on two dimensional data. it eliminates the need for external data storage through the use of the on-chip row buffers which are programmable for row lengths up to 1024 pixels. there are internal register banks for storing two independent 3 x 3 ?lter kernels, thus facilitating the implementation of adaptive ?lters and multiple ?lter operations on the same data. the pixel data path also includes an on-chip alu for performing real-time arithmetic and logical pixel point operations. data is provided to the HSP48908 in a raster scan noninterlaced fashion, and is internally buffered on images up to 1024 pixels wide for the 3 x 3 convolution operation. images with larger rows and convolution with larger kernel sizes can be accommodated by using external row buffers and/or multiple HSP48908s. coef?cient and pixel input data are 8-bit signed or unsigned integers, and the 20-bit convolver output guarantees no over?ow for kernel sizes up to 4 x 4. larger kernel sizes can be implemented however, since the ?lter coef?cients will normally be less than their maximum 8-bit values. the HSP48908 is manufactured using an advanced cmos process, and is a low power fully static design. the con?guration of the device is controlled through a standard microprocessor interface and all inputs/outputs are ttl compatible. features ? single chip 3 x 3 kernel convolution ? programmable on-chip row buffers ? dc to 32mhz clock rate ? cascadable for larger kernels and images ? on-chip 8-bit alu ? dual coef?cient mask registers, switchable in a single clock cycle ? 8-bit signed or unsigned input and coef?cient data ? 20-bit extended precision output ? standard m p interface ? low power cmos applications ? image filtering ? edge detection ? adaptive filtering ? real time video filter ordering information part number temp. range ( o c) package pkg. no. HSP48908vc-20 0 to 70 100 ld mqfp q100x14x20 HSP48908vc-32 0 to 70 100 ld mqfp q100x14x20 HSP48908jc-20 0 to 70 84 ld plcc n84.1.15 HSP48908jc-32 0 to 70 84 ld plcc n84.1.15 HSP48908gc-20 0 to 70 84 ld pga g84.a HSP48908gc-32 0 to 0 84 ld pga g84.a data sheet may 1999
2 pinouts 84 pin pga top view 11 10 9 8 7 6 5 4 3 2 1 dout0 cas06 gnd cas02 gnd caso0 din3 din6 cin1 cin3 cin5 dout1 cas07 cin4 cin6 gnd dout2 cin7 cin8 dout5 dout4 gnd clk dout6 dout9 v cc a1 dout8 gnd a2 cs dout10 dout11 ealu a0 dout12 dout14 casi13 casi16 dout13 gnd dout16 dout19 frame v cc casi14 casi7 casi10 casi11 casi14 dout17 dout18 gnd casi0 reset casi13 casi16 casi18 casi9 cas04 cas03 cas01 oe din1 din2 din5 din7 cin0 bcdef gh jkl a cas06 dout15 v cc din0 din4 dout3 dout7 v cc casi12 casi1 casi2 casi6 cin9 hold l0 cin2 HSP48908
3 84 lead plcc top view pinouts (continued) cin2 cin1 cin0 din7 din6 din5 din4 din3 din2 din1 din0 v cc oe gnd caso0 caso1 caso2 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 caso3 caso4 caso5 gnd 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 casi11 casi10 casi9 casi8 casi7 casi6 casi5 casi4 casi3 v cc casi2 casi1 casi0 frame reset gnd dout19 dout18 dout17 dout15 dout16 cin3 cin4 cin5 cin6 cin7 cin8 cin9 gnd clk v cc hold ld cs a2 a1 a0 ealu casi15 casi14 casi13 casi12 caso6 caso7 dout0 dout1 dout2 gnd dout3 dout4 dout5 dout6 dout7 v cc dout8 gnd dou9 dout10 dout11 dout12 dout13 dout14 gnd HSP48908
4 100 lead mqfp top view pinouts (continued) 99 98 97 96 95 94 93 91 89 87 85 84 83 81 82 86 88 90 92 100 79 80 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 32 33 34 35 36 37 38 40 42 44 46 47 48 50 49 45 43 41 39 31 ld gnd clk v cc v cc hold cs a2 a1 a0 gnd din0 caso2 caso3 caso4 gnd dout12 dout13 dout14 gnd dout15 dout16 gnd dout11 dout17 dout18 dout19 casi2 gnd casi1 casi0 frame dout5 dout6 dout7 v cc dout8 gnd gnd dout9 dout10 v cc dout4 casi15 casi14 ealu v cc gnd v cc casi3 casi4 casi5 casi10 casi9 casi8 casi7 casi6 caso5 nc caso6 caso7 dout1 dout2 gnd gnd dout3 dout0 gnd cin2 nc nc cin3 cin4 cin6 cin5 cin7 cin8 cin9 cin1 casi13 casi12 casi11 nc nc reset caso1 caso0 gnd gnd oe v cc v cc din1 din2 din3 din4 din5 din6 din7 cin0 HSP48908
5 block diagram data delay z -1 z -1 z -1 z -1 z -1 z -1 alu register alu address decoder control logic row buffer row buffer r casio - 7 casio - 15 casio0 - 7 r 2:1 2:1 2:1 cascade mode cascade mode z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 h gidefabc z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 z -1 + + z -1 z -1 + + z -1 z -1 cascade mode z -1 2:1 douto - 19 z -1 shift internal clock casio - 15 16 20 20 3 0 a0 - 2 ld cs clock gen clk hold frame reset oe cin0 - 9 din0 - 7 HSP48908
6 pin descriptions name plcc pin type description v cc 21, 42, 63, 84 the +5v power supply pins. 0.1 m f capacitors between the v cc and gnd pins are recommended. gnd 19, 48, 54, 61, 69, 76, 82 the device ground. clk 20 i input and system clock. operations are synchronous with the rising edge of this clock signal. din-07 1-8 i pixel data input bus. this bus is used to provide the 8-bit pixel input data to the HSP48908. the data must be provided in a synchronous fashion, and is latched on the rising edge of the clk signal. cln0-9 9-18 i coef?cient input bus. this input bus is used to load the coef?cient mask register(s), the initializa- tion register, the row buffer length register and the alu microcode. it may also be used to pro- vide a second operand input to the alu. the de?nition of the cln0-9 bits is de?ned by the register address bits a0-2. the cin0-9 data is loaded to the addressed register through the use of the cs and ld inputs. dout0-19 49-53, 55-60, 62, 64-68, 70-72 0 output data bus. this 20-bit output port is used to provide the convolution result. the result is the sum of products of the input data samples and their corresponding coef?cients. the cascade inputs casl0-15 may also be added to the result by selecting the appropriate cascade mode in the initial- ization register. casio-15 29-41, 43-45 i cascade input bus. this bus is used for cascading multiple HSP48908s to allow convolution with larger kernels or row sizes. it may also be used to interface to external row buffers. the function of this bus is determined by the cascade mode bit (bit 0) of the initialization register. when this bit is set to a 0, the value on casi0-15 is left shifted and added to dout0-19. the amount of the shift is determined by bits 7-8 of the initialization register. while this mode is intended primarily for cas- cading, it may also be used to add an offset value, such as to increase the brightness of the con- volved image. when the cascade mode bit is set to a 1 , this bus is used for interfacing to external row buffers. in this mode the bus is divided into two 8-bit busses (casl0-7 and casl8-15), thus allowing two ad- ditional pixel data inputs. the cascade data is sent directly to the internal multiplier array which al- lows for larger row sizes without using multiple HSP48908s. caso0-7 73-75, 77-81 0 cascade output bus. this bus is used primarily during cascading to handle larger frames and/or kernel sizes. this output data is the data on din0-7 delayed by twice the programmed internal row buffer length. frame 46 i f r ame is an asynchronous new frame or vertical sync input. a low on this input resets all internal circuitry except for the coef?cient, alu, amc, eor and int registers. thus, after a f r ame reset has occurred, a new frame of pixels may be convolved without reloading these registers. ealu 28 i enable alu input. this control line gates the clock to the alu register. when it is high, the data on cin0-7 is loaded on the next rising clock edge. when ealu is low, the last value loaded remains in the alu register. hold 22 i the hold input is used to gate the clock from all of the internal circuitry of the h5p48908. this signal is synchronous, is sampled on the rising edge of clk and takes effect on the following cycle. while this signal is active (high), the clock will have no effect on the HSP48908 and internal data will remain undisturbed. reset 47 i reset is an asynchronous signal which resets all internal circuitry of the HSP48908. all outputs are forced low in the reset state. oe 83 i output enable. the oe input controls the state of the output data bus (dout0-19). a low on this control line enables the port for output. when oe is high, the output drivers are in the high imped- ance state. processing is not interrupted by this pin. a0-2 25-27 i control register address. these lines are decoded to determine which register in the control logic is the destination for the data on the cln0-9 inputs. register loading is controlled by the a0-2, ld and cs inputs. ld 23 i load strobe. ld is used for loading the internal registers of the HSP48908. when cs and ld are active, the rising edge of ld will latch the cin0-7 data into the register speci?ed by a0-2. cs 24 i chip select. the chip select input enables loading of the internal registers. when cs is low, the a0-2 address lines are decoded to determine the meaning of the data on the cin0-7 bus. the rising edge of ld will then load the addressed register. HSP48908
7 functional description the HSP48908 two-dimensional convolver performs convolution of 3 x 3 ?lter kernels. it accepts the image data in raster scan, non-interlaced format, convolves it with the ?lter kernel and outputs the ?ltered image. the input and ?lter kernel data are both 8 bits, while the output data is 20 bits to prevent over?ow during the convolution operation. the HSP48908 has internal storage for two 3 x 3 ?lter kernels and is capable of buffering two 1024 x 8-bit rows for true single chip operation at video frame rates. an 8-bit alu in the input pixel data path allows the user to perform arithmetic and logical operations on the input data in real time during the convolution. multiple devices can also be cascaded together for larger kernel convolution, larger frame sizes and increased precision. image data is input to the convolver via the din0-7 bus. the data is then operated on by the alu, stored in the row buffers and convolved with the 3 x 3 array of ?lter coef?cients. the resultant output data is then latched into the output register. the row buffers are preprogrammed to the length of one row of the input image to enable the user to input the image data one pixel at a time in raster scan format without having to provide external storage. initialization of the convolver is done using the cln0-7 bus to load con?guration data, such as the ?lter kernel(s) and the length of the row buffers. the address lines a0-2 are used to address the internal registers for initialization. the con?guration data is loaded using the a0-2, cin0-9, cs and ld controls as address, data, chip select and write enable, respectively. this interface is compatible with standard microprocessors without the use of any additional glue logic. filtered image data comes out of the convolver over the dout0-1 9 bus. this output bus is 20 bits wide to provide room for growth during the convolution operation. the 20-bit bus will allow the use of up to 4 x 4 kernels (using multiple 48908s) without over?ow. however, in practical applications, much larger kernel sizes can be implemented without over?ow since the ?lter coef?cients are typically much smaller than 8-bit full scale values. dout0-19 is also a registered, three state bus to facilitate cascading multiple chips and to allow the HSP48908 to reside on a standard microprocessor system bus. multiple convolvers can also be cascaded together for kernel sizes larger than 3 x 3 and for convolution on images with row lengths longer than 1024 pixels. the maximum kernel size is dependent upon the magnitude of the image data and the coef?cients in a given application; care must always be taken with very large kernel sizes to prevent over?ow of the 20-bit output. data input image data coming into the 2d convolver passes through a programmable pipeline delay before being sent to the alu. the amount of delay (1 to 4 clock cycles) is set in the initialization register during con?guration setup (see control logic). delays greater than one are used primarily in cascading multiple HSP48908s to align data sequences for proper output (see operation). arithmetic logic unit the on-chip alu provides the user with the capability of performing pixel point operations on incoming image data. depending on the instruction in the alu microcode register, the alu can perform any one of 19 arithmetic and logical functions, and shift the resulting number left or right by up to 3 bits. tables 1 and 2 show the available alu functions and the 10-bit associated microcode to be loaded into the alu microcode register. note that the shifts take place on the output of the alu and are completely independent of the logical or arithmetic operation being performed. the ?rst input (a) of the alu is taken from the pixel input bus (dln0- 7). the second input (b) is taken from the alu register. the alu register is loaded via the cln0-7 bus while the ealu control line is valid (see ealu). table 1. alu shift operations alu microcode register register bit operation 987 0 0 0 no shift (default) 0 0 1 shift right 1 0 1 0 shift right 2 0 1 1 shift right 3 i 0 0 shift left 1 1 0 1 shift left 2 1 1 0 shift left 3 1 1 1 not valid table 2. alu pixel operations register bit operation 6543210 0000000 logical (00000000) 1111000 logical (11111111) 0011000 logical (a) (default) 0101000 logical (b) 1100000 logical ( a) 1010000 logical ( b) 0110001 arithmetic (a + b) 1001010 arithmetic (a -b) 1001100 arithmetic (b -a) 0001000 logical (a and b) 0010000 logical (a and b) HSP48908
8 ealu the ealu control pin enables loading of the alu register. while the ealu line is high, the data on cln0-7 is latched into the alu register on the rising edge of clk. when ealu goes low, the current value in the alu register is held until ealu is again asserted. note that the alu loading operation makes use of the cln0-7 inputs, but is completely independent of cs and ld. therefore, in order to prevent overwriting an internal register, care must be taken to ensure that cs and ld are not active during an ealu cycle. programmable row buffers the programmable row buffers are used for buffering raster input data for the convolution operation. they can be thought of as programmable shift registers which can each store up to 1024 8-bit values, thus, delaying each pixel by up to 1024 clock cycles. functionally, each row buffer can be represented as a set of registers connected as a 1024 x 8-bit serial shift register. the output of each buffer can be represented by the equation q = d(n-r), where q is the row buffer output, d is the buffer input, n is the current clock cycle and r is the preprogrammed row length of the input image. since the two buffers are connected in series, the data at the cascade outputs (caso0-7) is delayed by two row delays and may be used for cascading multiple convolvers for larger kernel sizes and/or row lengths. the programmable row buffers can also be bypassed by selecting the appropriate cascade mode in the initialization register. this mode allows the use of external row buffers for convolving with row lengths longer than 1024 pixels. 8-bit multiplier array the multiplier array consists of nine 8 x 8 multipliers. each multiplier forms the product of a ?lter coef?cient with a corresponding pixel in the input image. input and coef?cient data may be in either twos complement or unsigned integer format. the nine coef?cients form a 3 x 3 ?lter kernel which is multiplied by the input pixel data and summed to form a sum of products for implementation of the convolution operation as shown below: output = (a x p1) + (b x p2) + (c x p3) + (d x p4) + (e x p5) + (f x p6) + (g x p7) + (h x p8) + (l x p9) control logic the control logic (figure 1) contains the alu microcode register, the initialization register, the row length register, and the coef?cient registers. the control logic is updated by placing data on the cin0-9 bus and using the a0-2, cs and ld control lines to write to the addressed register (see address decoder). all of the control logic registers are loaded with their default values on reset, and are unaffected by frame. alu microcode register the alu microcode register is used to store the command word for the alu. the alu command word is a 10-bit instruction divided into two ?elds: the lower 7 bits determine the alu operation and the upper 3 bits specify the number of shifts which occur. the alu command words are de?ned in tables 1 and 2 (see alu section). 0100000 logical ( a and b) 0111000 logical (a or b) 1011000 logical (a or b) 1101000 logical ( a or b) 1110000 logical (a nand b) 1000000 logical (an or b) 0110000 logical (a xor b) 1001000 logical (a xnor b) table 2. alu pixel operations (continued) register bit operation 6543210 input data filter kernel p1 p2 p3 a b c p4 p5 p6 d e f p7 p8 p9 g h i HSP48908
9 encr1 address decode encr0 cas cr1 cr0 lmc eor a0 - 2 3 ld cs alu microcode register (amc) 10 alu microcode lmc initialization register (int) initialization data 8 row length register (rlr) 10 row length (r) cas eor e i 0 e h 0 e g 0 e f 0 e e 0 e d 0 e c 0 e b 0 e a 0 e i 1 e h 1 e g 1 e f 1 e e 1 e d 1 e c 1 e b 1 e a 1 coefficient register 0 ihgfedcba coefficient register 1 cr o cr1 encr1 encr o sq q r cin0 - 9 figure 1. control logic block diagram HSP48908
10 initialization register the initialization register is used to appropriately con?gure the convolver for a particular application. it is loaded through the use of the cln0-7 bus along with the cs an ld inputs. bit 0 de?nes the type of cascade mode to be used; bits 1 and 2 select the number of delays to be included in the input pixel data path; bits 3 and 4 de?ne the input and coef?cient data format; bits 5 and 6 determine the type of rounding to occur on the dout0-19 bus; bits 7 an 8 de?ne the shift applied to the cascade input data. the complete de?nition of the initialization register bits is give in table 3. row length register the row length register is used to store the programmed number of delays for the internal row buffers. the programmed delay is set equal to the row length (r) of the input image. the input pixel data is stored in the row buffers to allow corresponding pixels of adjacent rows to be synchronously sent to the multiplier array for the convolution operation. the row length register is programmable with the values from 0 to 1023, with 0 de?ned as a row length of 1024. row lengths of 1 or 2 lead to meaningless results for a 3x3kernelconv olution, while a row length of 3 de?n e1x9 ?lter (see operation section). the row length register is written through the use of a0-2, cs and ld. once the row length register has been loaded, the convolver must reset before a new row length can be entered, or else new value will be ignored. after reset returns high, user has 1024 cycles of clk to load the row length register. after 1024 clk cycles, the row length register is automatically set to 0 (row length = 1024) and further writes to this register are ignored. coef?cient registers (creg0, creg1) the control logic contains two coef?cient register banks cr eg0 and creg1. each of these register banks is capable of storing nine 8-bit ?lter coef?cient values (3 x 3 kernel). the output of the registers are connected to the coef?cient input of the corresponding multiplier in the 3 x 3 multiplier array (designated a through i). the register bank to be used for the convolution is selectable by writing to the appropriate address (see address decoder). all registers in a given bank are enabled simultaneously, and one of the banks is always active. for most applications, only one of the register banks is necessary. the user can simply load creg0 after power up, and use it for the entire convolution operation. (creg0 is the default register). the alternate register bank allows the user to maintain two sets of ?lter coef?cients and switch between them in real time. the coef?cient masks are loaded via the cin bus by using a0-2, cs and ld. the selection of the particular register bank to be used in processing is also done by writing to the appropriate address (see address decoder). for example, if creg0 is being used to provide coef?cients to the multipliers, creg1 can be updated at a low rate by an external processor; then at the proper time, creg1 can be selected, so that the new coef?cient mask is used to process the data. thus, no clock cycles have been lost when changing between alternate 3 x 3 ?lter kernels. the nine coef?cients must be loaded sequentially over the cln0-7 bus from a to i. the address of creg0 or creg1 is placed on a0-2, and then the nine coef?cients are written to the corresponding coef?cient register one at a time by using the cs and ld inputs. address decoder the address decoder (see figure 1) is used for writing to the control logic of the HSP48908. loading an internal register is done by selecting the destination register with the a0-2 address lines, placing the data on cin0-9, asserting the cs and ld control lines. when either cs or ld goes high, the data on the cin0-9 lines is latched into the addressed register. the address map for the a0-2 bus is shown in table 4. while loading of the control logic registers is asynchronous to clk, the target register in the control logic table 3. initialization register definition initialization register bit 0 function = cascade mode 0 multiplier input from internal row buffers. 1 multiplier input from external buffers. 2 bit 1 function = input data delay 0 0 no data delay registers used. 0 1 one data delay register used. 1 0 two data delay registers used. 1 1 three data delay registers used. bit 3 function = input data format 0 unsigned integer format. 1 twos complement format. bit 4 function = coefficient data format 0 unsigned integer format. 1 twos complement format. 6 bit 5 function = output rounding 0 0 no rounding. 0 1 round to 16 bits (i.e., dout19-4). 1 0 round to 8 bits (i.e., dout19-12). 1 1 not valid. 8 bit 7 function = casi0-15 input shift 0 0 no shift. 0 1 shift casi0-15 left two. 1 0 shift casi0-15 left four. 1 1 shift casi0-15 left eight. HSP48908
11 is being read synchronous to the internal clock. therefore, care must be taken when modifying the convolver setup parameters during processing to avoid changing the contents of the registers near a rising edge of clk. the required setup time relative to clk is given by the speci?cation tlcs. for example, in order to change the active coef?cient register from creg0 to creg1 during an active convolution operation, a write will be performed to the address for selecting creg1 for internal processing (a2 -0 = 110). in order to provide proper uninterrupted operation, ld should be deasserted at least tlcs prior to the next rising edge of clk. failure to meet this setup time may result in unpredictable results on the output of the convolver for one clock cycle. keep in mind that this requirement applies only to the case where changes are being made in the control logic during an active convolution operation. in a typical convolver con?guration routine, this speci?cation would not be applicable. cascade i/o cascade input the cascade input lines (casl0-15) have two primary functions. the ?rst is used to allow convolutions with kernel sizes larger than 3 x 3. this can be implemented by connecting the dout bus of one convolver to the cascade inputs of another. the second function is for convolution on images wider than 1024 pixels. this type of operation can be implemented by using external row buffers to supply the pixel input data to the casl0-15 inputs. the cascade input functions are determined by initialization register bit 0. when this bit is set to a 0, the cascade input data is added to the convolver output. in this manner, multiple convolvers can be used to implement larger kernel convolution. when initialization register bit 0 is 1, the data on casl0-15 is divided into two 8-bit portions and is sent to the 3 x 3 multiplier array (refer to block diagram). this mode of operation allows the use of external row buffers for convolution of images with row sizes larger than 1024. examples of these con?gurations are given in the operations section of this speci?cation. the data on the cascade inputs (casl0-15) can also be left shifted by 0, 2, 4, or 8 bits. the amount of shift is determined by bits 7 and 8 of the initialization register (see table 3). casl0-15 is shifted by the speci?ed number of bits and is added to the 20-bit output dout 0-19. the shifting function provides a method for cascading multiple HSP48908s and allowing a selectable amount of output growth while maximizing the resolution of the convolver result. the cascade inputs can also be used as a simple way to add an offset to the convolved image. bit 0 of the con?guration register would be set to 0, and the desired offset placed on the casl0-15 inputs. while multiple offsets can be used and changed during the convolution operation, note that the required data setup and hold times with respect to clk (tds and tdh) must be met. cascade output the cascade output lines (caso0-7) are outputs from the second row buffer. data at these outputs is the input pixel data delayed by two times the preprogrammed value in the row length register. the cascade outputs are used to cascade multiple convolvers by connecting the cascade outputs of one device to the data inputs of another (see operation section). control signals hold the hold control input provides the ability to disable internal clock and stop all operations temporarily. hold is sampled on the rising edge of clk and takes effect during the following clock cycle (refer to figure 2). this signal can be used to momentarily ignore data at the input of the convolver while maintaining its current output data and operational state. reset the reset signal initializes all internal ?ip ?ops and registers in the HSP48908. it is an asynchronous signal, and the convolver will remain in the reset state as long as reset is asserted. on reset, all internal registers are set to zero or their default values, and all outputs are forced low. following a reset, the default values in the internal registers will de?ne the following mode of operation: internal row buffers used, line length = 1024, no input data delay, logical table 4. address map control logic address map a2-0 function 000 load row length register (rlr). 001 load alu microcode register (amc). 010 load coefficient register 0 (creg0). 011 load coefficient register 1 (creg1). 100 load initialization register (int). 101 select creg0 for internal processing. 110 select creg1 for internal processing. 111 no operation. hold clk internal clock figure 2. hold operation HSP48908
12 a operation: output of alu = a input (din0-7) output rounding and unsigned input data format the convolver can be reset at any time, but must be reset before updating the row length register in order to provide proper operation. after reset returns high, the user has 1024 cycles of clk to load the row length register. after 1024 olk cycles, the row length register is automatically set to 0 (row length = 1024) and further writes to this register are ignored. frame this frame input initializes all internal ?ip ?ops and registers except for the coef?cient, alu, alu microcode, row length, and initialization registers. it is used to reset the convolver between video frames and eliminates the need to reinitialize the entire convolver or reload the coef?cients. frame is an asynchronous input and may occur at any time. however, it must be deasserted at least tfs ns prior to the rising clock edge that is to begin operation for the next frame. while frame is asserted, the registers and ?ip- ?ops will remain in the reset state. operation the HSP48908 has three basic modes of operation: single chip mode, operation with external row buffers and multiple devices cascaded together for larger convolution kernels and/or longer row lengths. the mode of operation is de?ned by the contents of the initialization register, and can be modi?ed at any time by a microprocessor or other external means. single chip mode a single HSP48908 can be used to perform 3 x 3 convolution on 8-bit image data with row lengths up to 1024. a block diagram of this con?guration is shown in figure 3. in this mode of operation, the image data is input into the dln0-7 bus in a raster scan order starting with the upper left pixel. to perform the convolution operation, a group of nine image pixels is multiplied by th e3x3arrayof ?lter coef?cients and their products are summed and sent to the output. for the example in figure 3, the pixel value in the output image at location (m, n) is given by: pout(m,n) (a x pm-1, n-1) + (b x pm-1, n) + (c x pm-1, n+1) + (d x pm, n-1) + (e x pm, n) + (f x pm, n+1) + (g x pm+1, n-1) + (h x pm+1, n)+ (i x pm+1, n+1) this process is continually repeated until the last pixel of the last row of the image has been input. it can then start again with the ?rst row of the next frame. the frame pin is used to clear the row buffers, multiplier input latches and douto19 registers between frames. the setup for single chip operation is straightforward. after reset, the convolver is con?gured for row lengths of 1024 pixels, no input data delay, no alu pixel point operations, no output rounding, and an unsigned input format. the user can change this default setup by loading new values into the alu microcode, initialization and row length registers. reset also clears the coef?cient registers and creg0 is selected for internal processing. the user can now load the coef?cients one at a time from a to i, via the cln0-7 inputs and the ld and cs control lines. multiple ?lter kernels can also be used on the same image data using the dual coef?cient registers creg0 and creg1. this type of ?ltering is used when the characteristics of the input pixel data change over the image in such a way that no single ?lter produces satisfactory results for the entire image. in order to ?lter such an image, the characteristics of the ?lter itself must change while the image is being processed. the HSP48908 can perform this function with the use of an external processor. the processor is used to calculate the required new ?lter coef?cients, loads them into the coef?cient register not in use, and selects the newly loaded coef?cient register at the proper time. the ?rst coef?cient register can then be loaded with new coef?cients in preparation for the next change. this can be carried out with no interruption in processing, provided that the new register is selected synchronous to the convolver clk signal. the HSP48908 can also operate as a one dimensional 9 tap fir ?lter by programming the row buffer length register with a value of 3 and setting the initialization register bit-0 to a 0. this con?guration will provide for nine sequential input values in the input to be multiplied by the coef?cient values in the selected coef?cient register and provide the proper ?ltered output. the equation for the output then becomes: d outn = a x dn -8 + b x dn -7 + c x d n-6 + d x d n-5 + e x d n-4 + f x d n-3 + g x d n-2 + h x d n-1 + i x d n use of external row buffers external row buffers may be used when frames with row sizes larger than 1024 pixels are desired. to use the HSP48908 in this mode, the cascade mode control bit (bit 0) of the initialization register is set to 1 to allow the data on filter kernel image data a b c pm-1, n -1 pm-1, n pm-1, n + 1 d e f pm, n -1 pm, n pm, n + 1 g h i pm + 1, n -1 pm + 1, n pm + 1, n + 1 figure 3. 3 x 3 kernel on an 8-bit, 1024 x n image HSP48908 image data clk 8 initialization data 20 filtered image HSP48908
13 the cascade inputs casi0-15 to go to the multiplier array. the inputs of one external row buffer (such as the hsp9500) are connected to the input data in parallel with the dln0-7 lines of the convolver; and its outputs are connected to the casl0-7 inputs (see figure 4). a second external row buffer is connected between the outputs of the ?rst row buffer and the casl8-15 inputs of the convolver. the convolution operation can then be performed by the HSP48908 in the same manner as the single chip mode. the row length in this con?guration is limited only by the maximum length of the external row buffers. note that when using the convolver in this con?guration, the programmable input data delays and alu will only operate on the data entering the din0-7 inputs (i.e., the bottom row of the 3 x 3 sum of products). if higher order ?lters or pixel point operations are required when using external row buffers, these functions must be implemented externally by the user. cascading multiple HSP48908s multiple HSP48908s are capable of being cascaded to per- form convolution on images with row lengths longer than 1024 pixels and with kernel sizes larger than 3 x 3. figure 5 illustrates the use of two HSP48908s to perform a 3 x 3 ker- nel convolution on a 2k x n frame. in this case, the cascade mode control bit (bit 0) of both initialization registers are set to a 0. the loading of the coef?cients is accomplished just as before. however, the 3 x 3 mask is divided into two por- tions for proper convolution output as follows: convolver #1 = def000ghl and convolver #2 = abc000000. the same con?guration can be used to perform 3 x 5 convolution on a 1k x n frame simply by setting up the coef?cients of the convolvers to implement the 3 x 5 mask as indicated below: in addition to larger frames, larger kernels can also be addressed through cascadability. an example of the con?guration for a 5 x 5 kernel convolution on a 1k x n frame is shown in figure 6. note that in this con?guration, convolver #2 incorporates a 3 clock cycle delay (z -3) and convolvers 3 and 4 incorporate 2 clock cycle delays (z -2) at their pixel inputs. these delays are required to ensure proper data alignment in the ?nal sum of products output of the cascaded convolvers. the number of delays required at the pixel input is programmable through the use of bits 1 and 2 of the initialization register (refer to table 3). image data filtered row buffer row buffer image data 20 8 din0 - 7 dout0 - 19 HSP48908 casi0 - 7 casi0 - 16 figure 4. using external row buffers with the HSP48908 3 x 3 filter kernel coefficient masks convolver #1 convolver #2 a b c d e f a b c d e f 0 0 0 0 0 0 g h i g h i 0 0 0 3 x 5 filter kernel convolver coefficient masks a b c g h i a b c d e f j k l d e f g h i m n o 0 0 0 j k l m n o image data filtered image data 8 din0 - 7 dout0 - 19 HSP48908 #1 casi0 - 15 figure 5. 3 x 3 kernal convolution on a 2k x n image caso0 - 7 din0 - 7 dout0 - 19 HSP48908 #2 casi0 - 15 caso0 - 7 z -2 20 HSP48908
14 in any of the cascade con?gurations, only 16 bits of the 20- bit output (dout0-19) can be connected to the 16 cascade inputs (casi0-15) of another convolver. which 16 bits are chosen, depends upon the amount of growth expected at the convolver output. the amount of growth is dependent on the input pixel data and the coef?cients selected for the convolution operation. the maximum possible growth is calculated in advance by the user, and the convolvers are set up to appropriately shift the cascade input data through the use of bits 7 and 8 of the initialization register (see cascade i/o). referring to figure 6, if the maximum growth out of convolver #1 extends into bit 16 or 17, then dout2-17 is connected to the cascade inputs of convolver #3, which is programmed to shift the input data left by two bits. likewise, if the data out of convolver #3 grows into bit 18 or 19, then dout4-19 are connected to the casi0-15 inputs of convolver #2, which is programmed to shift the input left by 4 bits. cascading for row sizes larger than 1024 combining large images with large kernels is accomplished by implementing external row buffers, external data delay registers and external adders. figure 7 illustrates a circuit for implementation of a5x5conv olution on a 2k x n image. the 5 x 5 coef?cient mask is again distributed among the four HSP48908s. the width of the dout path to be used in this case is dependent on the amount of resolution required and the amount of growth expected at the output. frame rate the total time to process an image is given by the formula: t = r x c/f, where: t = time to process a frame. r = number of rows in the image. c = number of pixels in a row. f = clock rate of the HSP48908. note that the size of the kernel does not enter into the equation. convolvers cascaded for larger kernels or larger frame sizes, as in the examples shown, process the image in the same amount of time as a single HSP48908 convolving the image with a 3 x 3 kernel. therefore, there is no performance degradation when cascading multiple HSP48908s. 5 x 5 filter kernel convolver coefficient masks a b c d e o k l o a b f g h l j o p q o f g k l m n o o u v 0 0 0 p q r s t u v w x y m n o c d e r s t h i j w x y 0 0 0 figure 6. 5 x 5 kernel convolution on a 1k x n image din0 - 7 dout0 - 19 HSP48908 #1 caso0 - 7 casi0 - 16 din0 - 7 dout0 - 19 HSP48908 #3 caso0 - 7 casi0 - 16 din0 - 7 dout0 - 19 HSP48908 #2 caso0 - 7 casi0 - 16 din0 - 7 dout0 - 19 HSP48908 #4 caso0 - 7 casi0 - 16 image data 8 z -2 z -3 z -2 filtered image data 20 image data z -1 z -1 z -1 + row buffer row buffer din0 - 7 dout0 - 19 casi0 - 7 casi8 - 15 din0 - 7 dout0 - 19 casi0 - 7 casi8 - 15 row buffer row buffer row buffer row buffer din0 - 7 dout0 - 19 casi0 - 7 casi8 - 15 din0 - 7 dout0 - 19 casi0 - 7 casi8 - 15 row buffer row buffer + + filtered image data figure 7. 5 x 5 kernel convolution on a 2k x n image HSP48908
15 absolute maximum ratings thermal information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0v input, output or i/o voltage applied . . . . .gnd -0.5v to v cc +0.5v esd classi?cation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to 70 o c voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.75v to 5.25v thermal resistance (typical, note 1) q ja ( o c/w) q jc ( o c/w) mqfp package . . . . . . . . . . . . . . . . . . 48.0 n/a plcc package . . . . . . . . . . . . . . . . . . 34.0 n/a pga package . . . . . . . . . . . . . . . . . . . 35.0 6.0 maximum junction temperature (t j ) mqfp package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 o c plcc package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 o c pga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 o c maximum storage temperature range . . . . . . . . . .-65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 o c (plcc, mqfp - lead tips only) die characteristics number of transistors or gates . . . . . . . . . . . . .190,000 transistors caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio nofthe device at these or any other conditions above those indicated in the operational sections of this speci?cation is not implied. note: 1. q ja is measured with the component mounted on an evaluation pc board in free air. dc electrical speci?cations v cc = 5.0v + 5%, t a = 0 o c to 70 o c parameter symbol test conditions min max units logical one input voltage v ih v cc = 5.25v 2.0 - v logical zero input voltage v il v cc = 4.75v - 0.8 v high level clock input v ihc v cc = 5.25v 3.0 - v low level clock input v ilc v cc = 4.75v - 0.8 v output high voltage v oh i oh = 400 m a, v cc = 4.75v 2.6 - v output low voltage v ol i ol = +2.0ma, v cc = 4.75v - 0.4 v input leakage current i i v in = v cc or gnd, v cc = 5.25v -10 10 m a i/o leakage current i o v out = v cc or gnd -10 10 m a standby power supply current i ccsb v in = v cc or gnd, v cc = 5.25v, outputs open - 500 m a operating power supply current i ccop f = 20mhz, v in = v cc or gnd, (note 2) - 140 ma input capacitance c in f = 1mhz, v cc = open, all measurements are referenced to device gnd (note 3). -10pf output capacitance c o -12pf notes: 2. power supply current is proportional to operating frequency. typical rating for i ccop is 7.0ma/mhz. 3. not tested, but characterized at initial design and at major process/design changes. HSP48908
16 ac electrical speci?cations v cc = 5.0v 5%, t a = 0 o c to 70 o c parameter symbol notes -32 (32mhz) -20 (20mhz) units min max min max clock period t cycle 31 - 50 - ns clock pulse width high t pwh 12 - 20 - ns clock pulse width low t pwl 13 - 20 - ns data input setup time t ds 13 - 14 - ns data input hold time t dh 0-0- ns clock to data out t out - 16 - 22 ns address setup time t as 13 - 13 - ns address hold time t ah 0-0- ns configuration data setup time t cds 14 - 16 - ns configuration data hold time t cdh 0-0- ns ld pulse width t lpw 12 - 20 - ns ld setup time t lcs note 4 25 - 30 - ns cin0-7 setup to clk t cs 14 - 16 - ns cs setup to ld t css 0-0- ns cin0-7 hold time from clk t ch 0-0- ns cs hold from ld t csh 0-0- ns reset pulse width t rpw 31 - 50 - ns frame setup to clock t fs note 5 21 - 25 - ns frame pulse width t fpw 31 - 50 - ns ealu setup time t es 12 - 14 - ns ealu hold time t eh 0-0- ns hold setup time t hs 11 - 12 - ns hold hold time t hh 1-1- ns output enable time t en note 6 - 16 - 22 ns output disable time t oz note 8 - 28 - 32 ns output rise time t r from 0.8v to 2.0v, note 8 -6-6ns output fall time t f from 2.0v to 0.8v, note 8 -6-6ns notes: 4. this specification applies only to the case where the HSP48908 is being written to during an active convolution cycle. it must be met in order to achieve predictable results at the next rising clock edge. in most applications, the configuration data and coefficients are loaded asynchronously and the t lcs specification may be disregarded. 5. while frame is an asynchronous signal, it must be deasserted a minimum of t fs ns prior to the rising clock edge which is to begin loading pixel data for a new frame. 6. transition is measured at 200mv from steady state voltage with loading as specified in test load circuit with c l = 40pf. 7. ac testing is performed as follows: input levels (clk input) 4.0 and 0v, input levels (all other inputs) 0v and 3.0v, timing reference levels (clk) = 2.0v, (others) = 1.5v; output load per test load circuit with c l = 40pf. output transition is measured at v oh 3 1.5v and v ol 1.5v. 8. controlled via design or process parameters and not directly tested. characterized upon initial design and after major process and/or design changes. HSP48908
17 test load circuit timing waveforms figure 8. functional timing figure 9. ealu timing figure 10. three-state control dut equivalent circuit 1.5v i ol i oh (note 9) c l s 1 notes: 9. includes stray and jig capacitance. 10. switch s 1 open for i ccsb and i ccop tests. t pwl t cycle t pwh t ds t dh t out t cs t ch clk din0 - 7, casi0 - 15 dout0 - 19, caso0 - 7 cin0 - 7 (to alu register) clk ealu t es t eh t en t oz oe dout0 - 19 1.7v 1.3v 1.5v HSP48908
18 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site http://www.intersil.com figure 11. configuration timing figure 12. synchronous load timing figure 13. hold timing figure 14. frame and reset timing timing waveforms (continued) t css t csh t as t ah t cdh t cds ld cs a0 - 2 cin0 - 9 t lpw clk ld t lcs clk hold internal clock t hs t hh t hs clk reset frame t rpw t fpw t fs HSP48908

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